dimmer light switch with up and down controls features: ? phase-lock loop synchronization allows use as a wall switch ? brightness control of incandescent lamps with touch plates (ls7534) or pushbutton switches (ls7535) ? dual controls eliminate confusion ? soft turn-on /turn-off ? controls the "duty cycle" from 23% to 88% (conduction angles for ac half-cycles between 41 and 159? respectively) ? operates at 50hz/60hz line frequency ? input for slow dimming ? +12v to +18v dc supply voltage (v ss - v dd ) ? ls7534, ls7535, ls7535ft (dip); - see figure 1 ls7534-s, ls7535-s, ls7535ft-s (soic) description: ls7534 and ls7535 are mos integrated circuits that are designed for brightness control of in- candescent lamps. the outputs of these ics control the brightness of a lamp by controlling the firing an- gle of a triac connected in series with the lamp. all internal timings are synchronized with the line fre- quency by means of a built-in phase-lock loop cir- cuit. the output occurs once every half-cycle of the line frequency. within the half-cycle, the output can be positioned anywhere between 159?conduction angle for maximum brightness and 41 conduction angle for minimum brightness in relation to the ac line frequency. the positioning of the output is con- trolled by applying the proper logic levels at the up and down inputs. these functions may be implemented with very few interface components which is described in the ap- plication examples (see fig. 5a and 5b). for touch plates, ls7534 is used (fig. 5a). for pushbutton switches, ls7535 is used (fig. 5b). in the following operating description of the applica- tion examples, an activation is touch for ls7534 and switch closure for ls7535. short activation (34ms to 325ms) up - when the lamp is off, if a short activation is applied to the up input, the lamp brightness is ramped up to full-on or to a previous brightness stored in the memory. the ramp- up time from off to full-on is 2.8 sec. the ramp-up time from off to any other brightness is proportionally shorter. when the lamp is on at any brightness, a short activation applied to the up input has no effect. down - if a short activation is applied to the down input, the lamp brightness is ramped down to off. the ramp-down time from full-on to off is 5.6 seconds. the ramp-down time from any other brightness is proportionally shorter. when the lamp is off, a short activation applied to the down input has no effect. long activation (greater than 334ms) up - if a long activation is applied to the up input, the lamp brightness ramps up from the pre-activation brightness as long as the activation is maintained or until the full bright- ness is reached. at full brightness any continued long ac- tivation has no further effect. down - if a long activation is applied to the down input, the lamp brightness is ramped down as long as the long ac- tivation is maintained or until the minimum brightness is reached. at minimum brightness, any continued long ac- tivation has no further effect. when the lamp is off, a long activation applied to the down input has no effect. pin assignment - top view lsi 1 2 3 4 8 7 6 5 ls7534 figure 1 trig v dd (-v ) down up v ss (+v) doze cap sync 7535- 111109-1 lsi/csi lsi computer sy stems, inc. 1235 walt whitman road, melville, ny 11747 (631) 271-0400 fax (631) 271-0405 u l a3800 ls7534, ls7535 ls7535ft nov. 2 009 application: ls7535 is ideal for use in electronic dimmers for ?mart-house?type applications because it is designed to be easily controlled by remote switches. ls7535ft note ls7535ft ramp-up and ramp-down times are instantaneous. otherwise, it functions the same as ls7535 .
up/down signal duration short long input 34ms to 325 ms more than 334ms up down pre-activation brightness off max. intermediate off max. intermediate post-activation brightness memory ** (see note 1) no change no change no change off * off * pre-activation brightness off max. intermediate off max. intermediate post-activation brightness increases from min. no change increases from pre- touch brightness no change decreases from max. decreases from pre- touch brightness * 5.6 second ramp-down from max. to off. ramp-down time from any other brightness is proportionally shorter. ** 2.8 second ramp-up from off to max. note 1: "memory" refers to the brightness stored in the memory. the brightness is stored in memory when the lamp is turned off by a short activation. first time after power-up, a short activation produces max. brightness. input/output description: v ss (pin 1) supply voltage positive terminal. doze (pin 2) a clock applied to this input causes the brightness to de- crease in equal increments with each negative transition of the clock. eventually, when the lamp becomes off, this input has no further effect. the lamp can be turned on again by activating the up input. for the transition from maximum brightness to off, a total of 83 clock pulses are needed at the doze input. when either the up or the down input is active, the doze input is disabled. cap (pin 3) the cap input is for external component connection for the pll filter capacitor. a capacitor of 0.047f 20% should be used at this input. sync (pin 4) the ac line frequency (50hz/60hz), when applied to this input, synchronizes all internal timings through a phase lock loop. the signal for this input may be obtained from the line voltage by employing the circuit arrangement shown in the application examples. up (pin 5) this input controls the turn-on and the conduction angle, ?, of the trig output. a description of this is provided in the description and table 1. for ls7534, a logic low level is the active level whereas for ls7535 a logic high level is the active level. ls7535 has an internal pull-down resistor of about 500k ohms on this input. down (pin 6) this input controls the turn-off and the conduction angle, ? of the trig output. a description of this is provided in the description and table 1. for ls7534, a logic low level is the active level, whereas for ls7535 a logic high level is the active level. ls7535 has an internal pull-down resistor of about 500k ohms on this input. v dd (pin 7) supply voltage negative terminal. trig (pin 8) the trig output provides a low level pulse occurring every half-cycle of the sync signal. the conduction angle, ? of the trig output can be varied within the range of 41 o to 159 o by means of either the up or the down input. table 1 7535-012703-2
absolute maximum ratings: parameter symbol value unit dc supply voltage v ss - v dd +20 v any input voltage v in v ss - 20 to v ss + 0.5 v operating temperature t a 0 to +80 ?c storage temperature t stg -65 to +150 ?c dc electrical characteristics: (t a = 25?c, all voltages referenced to v dd ) parameter symbol min typ max unit conditions supply voltage v ss +12 - +18 v - supply current i ss - 1.2 1.7 ma v ss = +15v, output off input voltages: doze lo v izl 0 - v ss - 6 v - doze hi v izh v ss - 2 - v ss v - sync lo v irl 0 - v ss - 9.5 v - sync hi v irh v ss - 5.5 - v ss v - up, down lo v iol 0 - v ss - 8 v - up, down hi v ioh v ss - 2 - v ss v - input current: sync, up, down hi i ih - - 110 ua with series 1.5m w resistor to 115 vac line sync, up, down lo i il - - 100 na - doze hi i ih - - 100 na - doze lo i il - - 100 na - trig hi v oh - v ss - v - trig lo v ol - v ss - 8 - v v ss = +15v trig sink current i os 50 - - ma v ss = +15v, v ol = v ss - 4v transient characteristics (see fig. 2 and 3) (all timings are based on fs = 60hz, unless otherwise specified.) parameter symbol min typ max unit sync frequency fs 40 - 70 hz up, down duration (short) ts 1 34 - 325 ms up, down duration (long) ts 2 334 - infinite ms ramp time, off to max t us - 2.8 - sec (up,short) ? ramp time, min to max t ul - 3.6 - sec (up,long) ramp time, max to min t ds - 5.6 - sec (down,short) ramp time, max to min t dl - 3.6 - sec (down,long) trig pulse width t w - 33 - ? trig conduction angle (see note) 41 - 159 degrees doze frequency f d 0 - 500 hz note: the phase delay caused by the typical rc network used between sync input and the ac line (see fig. 5a and fig. 5b) reduces the effective ?values by 8? 7535-012703-3
figure 3. output conduction angle, ? , vs up/down inputs note 1 . up/down input polarity shown is for ls7534. for ls7535, the polarity is reversed. note 2 . points a, d, e and k correspond to minimum brightness, where ? = 41?. points b, c, g and h correspond to maximum brightness, where ? = 159?. points denoted by m correspond to an arbitrary intermediate brightness. note 3 . points f, j and l correspond to ? = 64?. the ramp-up or ramp-down rate of ? changes at these points (upon long activation only) indicated by the discontinuity of the slopes. the interval e to f or j to k, in terms of time and angle, are 934ms and 23?, respectively. out ? sync t w t w 200 150 100 50 0 down up (degrees) 0 4 8 12 16 0 4 8 12 0 4 8 12 16 20 24 a b c d e f h k g j m l m t dl 334ms 334ms t s2 t s2 t s1 t s2 t s1 t s1 t s1 t us t ds t ul 334ms seconds figure 2. output conduction angle, 7535-012703-4
trig output driver digital com- parator brightness memory pointer phase lock loop control logic buf buf buf buf sync cap doze down up (+v) (-v) figure 4 ls7534/ls7535 block diagram 4 3 2 6 5 1 7 8 v ss v dd application examples : typical dimmer light switch circuit schematics are shown in fig. 5a (ls7534) and fig. 5b (ls7535). the brightness of the lamp is set by touching the up and down touch plates in fig. 5a and closure of the up and down switches in fig. 5b. the functions of different components are as follows: z, d1, r1, c2 and c5 produce the 15v dc supply for the chip. r2 and c4 filter and current limit the ac signal for the sync input. c3 is the filter capacitor for the internal pll. c1 and l are rfi filters. in fig. 5a, r3 and r4 set the touch sensitivity of the up and down inputs. in fig. 5b, r3 limits the current between vss and the up and down inputs upon closure of a switch. the resistor and diode connected between the chip output and the triac gate provides current limiting and isolation for the chip. the resistor is r5 in fig. 5a and r4 in fig. 5b. in fig. 5b, pcb layout may cause triac switching transients to be coupled to the up or down input which can have the effect of having a long switch closure lock-up at a certain phase angle output. in this case, capacitors c6 and c7 must be added as shown. the information included herein is believed to be accurate and reliable. however, lsi computer systems, inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7535-012703-5
p 115vac or 220vac n load c1 t l c2 r1 r2 a b r5 r3 c5 d1 1 2 3 4 8 7 6 5 r3 c3 c4 trig v dd down up v ss doze cap sync + see note 2 ls7534 doze circuit fig. 6a v ss dz up v dd r4 r4 r4 r4 down touch plate up touch plate down see note 1 figure 5a. typical ls7534 dimmer light switch g mt2 mt1 z d2 - 115vac c1 = 0.15?, 200v r4 = 2.7m w , 1/4w c2 = see c2 value table r5 = see r5 value table c3 = 0.047?, 25v d1, d2 = in4148 c4 = 470pf, 25v z = 15v, 1w (zener) c5 = 47?, 25v t = q4004l4 triac (typical) r1 = 270 w , 1w l = 100? (rfi filter) r2 = 1.5m w , 1/4w r3 = 1m w to 5m w , 1/4w (select for sensitivity) (1) for connection a. use 1/4 w for connection b. c2 value table r5 value table c2 = 0.33?, 200v, connection a r5 = 100 w , 1/4w, 25ma triac gate 7535-111109-6 notes: 1) when doze circuit is used, break pin 1 to pin 2 connection. 2) use connection a when neutral is not available. use connection b when neutral is available. (1) 220vac c1 = 0.15?, 400v r4 = 4.7m w , 1/4w c2 = see c2 value table r5 = see r5 value table c3 = 0.047?, 25v d1, d2 = in4148 c4 = 470pf, 25v z = 15v, 1w (zener) c5 = 47?, 25v t = q5004l4 triac (typical) r1 = 1k w , 2w l = 200? (rfi filter) r2 = 3.3m w , 1/4w r3 = 1m w to 5m w , 1/4w (select for sensitivity) (2) for connection a. use 1/4w for connection b. c2 value table r5 value table c2 = 0.22?, 400v, connection a r5 = 100 w , 1/4w, 25ma triac gate c2 = 0.10?, 400v, connection b r5 = 50 w , 1/4w, 50ma triac gate (2)
115vac c1 = 0.15?, 200v r2 = 1.5m w , 1/4w c2 = see c2 value table r3 = 27k w , 1/4w c3 = 0.047?, 25v r4 = see r4 value table c4 = 470pf, 25v d1, d2 = in4148 c5 = 47?, 25v z = 15v, 1w (zener) c6, c7 = 0.001?, 25v t = q4004l4 triac (typical) r1 = 270 w , 1w l = 100? (rfi filter) (1) for connection a. use 1/4w for connection b. c2 value table r4 value table c2 = 0.33?, 200v, connection a r4 = 100 w , 1/4w, 25ma triac gate c2 = 0.22?, 200v, connection b r4 = 50 w , 1/4w, 50ma triac gate p 115vac or 220vac n load c1 mt1 l z c2 r1 r2 a b r4 c5 d1 1 2 3 4 8 7 6 5 c3 c4 trig v dd down up v ss doze cap sync + see note 2 ls7535 doze circuit fig. 6b v ss dz up v dd down see note 1 figure 5b. typical ls7535 dimmer light switch g up r3 t mt2 down d2 - see note 3 c6 c7. notes: 1) when doze circuit is used, break pin 1 to pin 2 connection. 2) use connection a when neutral is not available. use connection b when neutral is available . 3) c6 and c7 may be required in some pcb layouts to eliminate coupling from triac circuitry. (1) (2) 220vac c1 = 0.15?, 400v r2 = 3.3m w , 1/4w c2 = see c2 value table r3 = 27k w , 1/4w c3 = 0.047?, 25v r4 = see r4 value table c4 = 470pf, 25v d1, d2 = in4148 c5 = 47?, 25v z = 15v, 1w (zener) c6, c7 = 0.001?, 25v t = q5004l4 triac (typical) r1 = 1k w , 2w l = 200? (rfi filter) ( 2) for connection a. use 1/4 w for connection b. c2 value table r4 value table c2 = 0.22?, 400v, connection a r4 = 100 w , 1/4w, 25ma triac gate c2 = 0.10?, 400v, connection b r4 = 50 w , 1/4w, 50ma triac gate 7535-111109-7
v ss up dn dz v dd figure 6a. doze circuit for ls7534 sense doze switch 4093 4093 4093 10f 330k 4093 mp58098 + - 3.3m 330k 3.3m note: all resistors 1/4w, all capacitors 25v v ss v dd doze switch 4093 4093 figure 6b. doze circuit for ls7535 4093 4093 + - dz sense 3.3m up dn in914 in914 3.3m 3.3m 10f note: all resistors 1/4 w, all capacitors 25v. doze circuit: (figures 6a and 6b) the doze circuits shown generate a slow clock (0.04hz) at the dz terminal. if the up/down inputs (figures 5a and 5b) are not activated, the sense node of the doze circuit sits at a logic high level. a momentary pressing of the doze switch sets the sr flip-flop, enabling the oscillator. every negative transition of the clock (dz terminal) causes the lamp brightness to be reduced by equal increments, un- til eventurally the lamp is shut- off. when the lamp is off, the oscillator has no further effect on the dimmer circuit. when the lamp is turned on again by activating the up input, the sr flip-flop is reset and the dz clock is turned off. when the doze circuit is used, the connection between doze input (pin 2) and vss (pin 1), as shown in figures 5a and 5b, should be removed. figure 7. operating description of a full-feature ls7535 wall switch see application note an 705 for the schematic dual control continuous dimmer with unique delayed off feature initial condition action result off short press on softly turns on to memory intensity (1) off long press on varies from min. intensity towards max. intensity (2) on long press on varies towards max. intensity (2) on long press off varies towards min. intensity (3) on short press off softly turns off on press auto-dim begins auto-dimming to off (4) auto-dimming short press on softly returns to memory intensity (5) auto-dimming long press on varies towards max. intensity (2) auto-dimming short press off softly turns off auto-dimming long press off varies towards min. intensity (3) auto-dimming press auto-dim no change auto-dimming none auto-dims to off (1) last intensity achieved before turn off is stored as memory intensity. (2) on (dim up) varies intensity towards maximum and stops there. (3) off (dim down) varies intensity towards minimum and stops there. (4) auto-dimming period controlled by rc components and intensity level when auto-dim is activated. (5) last intensity achieved before auto-dim started is stored as memory intensity. 7535-012703-8 on dim up off dim down auto dim
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